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Linear Delay-cell Design for Low-energy Delay Multiplication and Accumulation

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Document pages: 12 pages

Abstract: A practical deep neural network s (DNN) evaluation involves thousands ofmultiply-and-accumulate (MAC) operations. To extend DNN s superior inferencecapabilities to energy constrained devices, architectures and circuits thatminimize energy-per-MAC must be developed. In this respect, analog delay-basedMAC is advantageous due to reasons both extrinsic and intrinsic to the MACimplementation - (1) lower fixed-point precision requirement for a DNN sevaluation, (2) better dynamic range than charge-based accumulation, forsmaller technology nodes, and (3) simpler analog-digital interfacing.Implementing DNNs using delay-based MAC requires mixed-signal delay multipliersthat accept digitally stored weights and analog voltages as arguments. To thisend, a novel, linearly tune-able delay-cell is proposed, wherein, the delay isrealized using an inverted MOS capacitor s (C*) steady discharge from alinearly input-voltage dependent initial charge. The cell is analyticallymodeled, constraints for its functional validity are determined, andjitter-models are developed. Multiple cells with scaled delays, correspondingto each bit of the digital argument, must be cascaded to form the multiplier.To realize such bit-wise delay-scaling of the cells, a biasing circuit isproposed that generates sub-threshold gate-voltages to scale C* s dischargingrate, and thus area-expensive transistor width-scaling is avoided. For 130nmCMOS technology, the theoretical constraints and limits on jitter are used tofind the optimal design-point and quantify the jitter versusbits-per-multiplier trade-off. Schematic-level simulations show a worst-caseenergy-consumption close to the state-of-art, and thus, feasibility of thecell.

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