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Great opportunity to improve dgmosfet by using high mobility materials

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  • Save Nanoscience and Nanotechnology 2016, 6(1A): 47-54 DOI: 10.5923/c.nn.201601.09 Tremendous Opportunities to Improve DGMOSFET by High Mobility Materials Channel S. Slimani1,*, B. Djellouli2 1Faculty of Electrical and Computer Engineering, Mouloud Mammeri University (UMMTO), Tizi-Ouzou, Algeria 2Laboratoire de Modélisation et Méthodes de calcul LMMC, Algeria University of Saida, Algeria Abstract There has been significant effort in simulations to benchmark the performance of nanoscale DGMOSFET transistors using high mobility channel. Different architectures, substrate orientations and strain effects are investigated by several methods and approach for Ge PMOS. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge PMOS technology. A comparaison of Ge and Si as channel in the DGMOSFET has been carried out. Keywords SOI-DGMOSFET, CMOS, Quantum effects, Quantum-drift-diffusion, Local Fermi level, High mobility 1. Introduction Starting to attain adequate drive current for the highly scaled MOSFETs (below the 22nm technological node [1]), high transport channel materials (e.g., germanium or III-V thin channels on silicon) may be needed due to a smaller effective mass in Ge can potentially lead to higher carrier mobility and drive currents in Ge MOSFETs than in Si MOSFETs. Ge is particularly well suited for p-type devices, thanks to its high hole mobility which is about four times greater than that of silicon, as well as some processing related issues, such as dopant solubility and Fermi level pinning at the valence band. Ge MOSFETs with different gate dielectrics including HfO2 [2], ZrO2 [3], have been demonstrated. There has been significant effort in simulations to benchmark the performance of nanoscale Ge transistors. Different architectures, substrate orientations and strain effects are investigated by several research groups for Ge NMOS and PMOS. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. In this work we use the nextnano code to simulate a DG-MOSFET with high-k gate dielectric [17] and Ge channel. This simulation tool is based on the self-consistent solution of the Schrödinger, Poisson and current equations [4, 5]. The coupled Poisson-Schrödinger system is solved by an * Corresponding author: (S. Slimani) Published online at Copyright © 2016 Scientific & Academic Publishing. All Rights Reserved approximate quantum charge density, which is employed inside of Poisson’s equation in order to estimate the dependence of the density on the potential through Schrödinger’s equation. Using this estimator the coupling between both equations is much decreased and rapid convergence is achieved. The electronic structure is calculated within a single-band or multiband k .p envelope function approximation. The included model for the carrier transport is a Wentzel–Kramer–Brillouin (WKB)- type approach also known as quantum-drift-diffusion (QDD) method, where the carriers are locally in equilibrium, charactized by a local Fermi level [6, 7]. The main aim of this paper is to provide an insight by replacing Silicon in the channel by Ge using different dielectric constants. A comparaison of Ge has been made with both HfO2, ZrO2 and Si with SiO2. Current-voltage (I-V) curves are demonstrated by varying the channel doping concentration. The outline of the paper is as follows. Section II describes device structure. Section III presents some theoretical aspects. Section IV shows the simulation results using Quantum-drift-diffusion method. Section V concludes the paper. 2. Structure and Simulation Details Fig. 1 shows the structure of simulated device SOI DGMOSFET. The device parameters is summarised in table 1. This symmetric structure is characterized by p-type doped channel using Si and Ge channel of 6nm width. This channel is embedded between two heavily n-doped source and drain regions of length 10 nm that are connected to source and drain contacts. The junctions are assumed to be abrupt. The polysilicon gates are separated from the Si and 48 S. Slimani et al.: Tremendous Opportunities to Improve DGMOSFET by High Mobility Materials Channel the Ge channels by an oxide layer and the power supply voltage VDD is 0.7V. In order to highlight the performance of device at 22nm technological node and by using different channel doping, we have carried out the calculation by varying different dielectrics ZrO2 and HfO2 while maintaining the same channel width (6 nm) and oxide thickness (1.1nm). The channel doping (NA) is changed to maintain the constant Vth which is tabulated in Table 1. VGS Top gate Oxide TChanne l Source Channel Drain VDS (n+) P type variable (n+) LG Oxide Bot gate VGS Figure 1. Symmetrical DG-MOSFET considered in this work Table 1. Device parameters taken for design Parameters Gate Length Gate oxide thickness Source/Drain Doping Channel doping Value 18nm 1.1nm 1020cm-3 0.1×1015,cm-3,1×1015 cm-3, 10×1015 cm-3 3. Calculation Method The drift-diffusion model is widely used for simulation of carrier transport in semiconductors this model had been taken for simulating the electronic structure within Nextnano3 [8, 9], and is defined by the basic semiconductor equations. Current density for electrons is given by: The Poisson equation: ∇2ψ = q ⋅ (n − p − c) ε (1) The current continuity equation for electrons and holes: ∇J n − q⋅ ∂n ∂t = q⋅R ∇J p − q⋅ ∂p ∂t = −q ⋅ R (2) The current relations for electrons and holes: Jn = q ⋅ n ⋅ µn ⋅ En + q ⋅ Dn ⋅ ∇n J p = q⋅ p ⋅ µ p ⋅ E p − q⋅ Dp ⋅∇ p (3) The charge density is calculated for a given applied voltage by assuming the carriers to be in a local equilibrium that is characterized by energy-band dependent local quasi-Fermi levels EFc(x) for charge carriers of type c (i.e. in the simplest case, one for holes and one for electrons), ????????(????) = ∑????�ψ????????(????)�2 ???? �????????????????(????????)????−????????????� (4) These local quasi-Fermi levels are determined by global current conservation ∇ ∙ ???????? = 0 , where the current is assumed to be given by the semi-classical relation : ????????(????) = µ????????????(????)∇EFc(x) (5) The carrier wave functions ψ???????? and energies ???????????? are calculated by solving the multiband Schrodinger-Poisson equation [4]. The EOT used in this work is that obtained by classical Electrostatic theory in planar devices where: ???????????? = ????????????????2 ????ℎ????????ℎ−???? ????ℎ????????ℎ−???? (6) The SiO2, HfO2 and ZrO2 permittivities are 3.9,21.2 and 25 respectively. Due to the increase of the gate dielectric thickness, the leakage current ???????? by tunnel effect is then significantly reduced. Indeed, this one decrease exponentially with the gate dielectric thickness ???????? = ???? ????ℎ2 ????????ℎ−???? ???????????? �−2????ℎ????????ℎ−???? �2????ℏ2∗ ???? �???????? − ????ℎ????????2ℎ−????�� (7) with: A: constant m*: carriers effective mass q: electron charge ħ: Planck constant ФB : unevenness between the level of the Si conduction band and high k material. ????ℎ????????ℎ−???? : Loss of voltage through the dielectric. For long channel devices, the sub-threshold slope, which is the gate voltage excursion required to increase the drain current by one decade in the weak inversion regime, results from the voltage sharing between the gate dielectrics and the depletion region of the transistor. It is expressed as: ???? = ???????? ???? ln(10) �1 + ????????????????????????????� , (8) where k is the Boltzmann constant, q the elementary charge, T the temperature, ???????????????? and ???????????? the depletion and the gate oxide capacitances, respectively. 4. Results The off-state current is influenced by several parameters such as channel physical dimensions, source/drain junction depth, thickness of gate oxide, channel/surface doping profile and supply voltage (Vdd) [17]. To overcome these impact, we explore the possibility of using Ge as a channel material in p-type MOSFETs with Schottky barrier (SB) contacts. As the Ge concentration is increased, drain current is also increased because of the enhanced mobility. Fig2 shows the IDS versus VGS curves at constant VDS of 0.7V for different channel materials for EOT=1.1nm, HfO2 Nanoscience and Nanotechnology 2016, 6(1A): 47-54 49 and ZrO2 gate dielectrics with Ge shows higher drain current but it requires lower threshold voltage which results short channel effects (SCEs) take dominance, therefore germanium material channel are preferable for given threshold voltage as shown in the inset of Fig2. OFF current varies sharply with permittivity with Ge channel. It was revealed that the drain-current for the Ge channel DG MOSFETs was tremendously improved when compared to the Si channel. Also the OFF current for undoped channel raise as the permittivity decrease and its more higher than doped channel. The off-state current Ioff at VGS=0V When applying HfO2 is 0.169A/m In the case of ZrO2 dielectric and Ge channel, the off-state current Ioff at VGS=0V is 0.121A/m. and is 1,09A/m in the case of SiO2 with Si channel. The HfO2Ioff and ZrO2 Ioff is much less than SiO2. With increase in channel doping Off-state current get increses. (Table 2). Table 2. Variation of Ioff with channel doping Channel Doping conc. (cm-3) Ioff for HfO2 A/m Ioff for ZrO2 A/m Ioff for SiO2 A/m Witout doping 0.1×1015 1×1015 10×1015 0,492 0,126 0,169 0, 475 0.313 0.111 0.121 0.305 3,8705 1,009 1,091 1,1089 The threshold voltage from IDS–VGS characteristics at VDS = 0.7V. is increasing with the increment of permittivity using Ge channel (Fig.3). The threshold voltage lowering is increasing continuously with the channel Doping Fig.3 shows the variation of threshold with different doping levels [16]. HfO2 and ZrO2 gate dielectrics with Ge at 10×1015 level doping show higher drain current but it require lower threshold voltage thus it is possible to increase subthreshold effects. So we can have desired value of the threshold voltage by varying the channel doping. But high channel doping cannot be done as it leads to gate induced drain leakage. The suitable value of channel doping is 1015 and value of threshold voltage at this doping level are106.8 mV for the ZrO2 which is optimum value of threshold voltage for the gate length of 18 nm. Therefore, one using Silicon with SiO2, it will be higher (Figure 4). Table 3. Variation of SS with channel doping Channel Doping conc. (cm-3) Witout doping 0.1×1015 1×1015 10×1015 SS for HfO2 mV/decade-1 78.98 65.05 67.16 69.68 SS for ZrO2 75.8 55.48 59.7 62.2 SS for SiO2 188.4 180.21 183.1 186.4 103 HfO2 ZrO2 102 LG=18nm,TGe=6nm EOT=1.1nm 101 1000 100 100 10-1 0,0 0,1 0,2 IDS(A/m) 10 1 0,1 0,0 0,1 0,2 0,3 0,4 VG(V) HfO2 ZrO2 LG=18nm,TGe=6nm EOT=1.1nm LG=18nm,TSIO2=6nm EOT=1.1nm 0,3 0,4 0,5 0,6 VG(V) 0,5 0,6 0,7 0,7 Figure 2. IDS versus VGS characteristics of DGMOSFETs for HfO2and ZrO2 50 S. Slimani et al.: Tremendous Opportunities to Improve DGMOSFET by High Mobility Materials Channel Threshold voltage(V) 0,15 Ge channel with HfO2 Ge channel with ZrO2 Si channel with SiO2 0,10 0 2 4 6 8 10 Channel Doping (cm-3) Figure 3. Threshold voltage versus Channel doping For the various results obtained using simulation approach, lower value of subthreshold swing is desirable so lightly doped channel devices with high permittivity are preferred over doped and undoped channel devices. As we increase the channel doping, subthreshold swing increases linearly as shown in Table 4. Figure 5 shows the subthreshold region of MOSFETs which has a significant high gain due to exponential behavior of the drain current thus gives rise to higher transconductance generation factor (Gm/ID) in the subthreshold regime [10, 11]. gm and Gm/ID are directly dependent on the drain current. So, the structure having Ge channel gives rise to higher values of transconductance, maximum value of transconductance and maximum value of output conductance are outlined in table4.By comparing these values while dopping channel varying from 0.1×1015 to 10×1015 the Tansconductance (Gm) is decreased by 5.4% for SiO2 and 24.7% for ZrO2 And 27,9% for HfO2. Gd is increased by 28.8% for HfO2 and 10. 3% forZrO2 and 35.5%f or SiO2.we can see the variation Gm and Gd in Fig.6 (plots Gm versus channel doping (in the inset Gd versus channel doping)). Higher transconductance means gate has more control over the charge in the channel (Table 4). From Fig.5 it’s clear that tas the Vgs increases the Gm / Id decreases In this figure, the maximum performance can be obtained in ZrO2 Gm / Id ratio by comparing with HfO2 and SiO2. ON-State current, decides the driving capability of the device. It is defined as drain to source current when Vgs=Vdd and Vds= Vdd. Fig.7 demonstrates the Id-Vd characteristics for Si and Ge channel DG MOSFETs. Here, the current in Ge channels is increased compared to Si channel, due to the enhanced mobility. It means the mobility of charge carrier in Ge channel is higher due to which they give higher Ion. saturation occurs around 0.28 volts to 0.41 volts for all the channel materials. Si and SiO2 gets saturated at almost at the same voltage of 0.28 volts Ge with ZrO2 and HfO2 get saturated at 0.41V. have higher saturation current around 935A/m On the whole this figure indicates that Ge using high permittivity have more current density as compared to Si, which is highly desired for channel material. Table 4 given shows the drive current variation for different doping levels. We can see the decrease of ION as channel doping increase. The drain current is dependent on the mobility of carriers which is controlled by the doping concentrations. When the channel doping is kept high which results a lower drain current then the device having higher NA. Ge MOSFETs with different gate dielectrics including HfO2 [12, 13], ZrO2 [13, 14, 15], the high permittivity increases Ion and decrease Ioff. More ever the Ion and Ioff for HfO2 and ZrO2 dielectric are summarized in Tables 2 and 5. The Ion/Ioff current ratio represents the power consumption of a device. As we increase the channel doping drive current reduces almost linearly, but off state current decreases exponentially. This leads to increase in Ion/Ioff ratio very sharply as shown in Figure 8. Figure. 9 shows gate direct tunneling current as function of channel doping for VDS=VDD=0.7V, VGS=0.7V. The gate direct tunneling current takes a minimum value in the case of silicium and maximum value in the case of ZrO2. So If we increase channel doping and permittivity one parameter get improved while other get worse. The improvement in electron density has been investigated in terms of channel doping in Fig.10; this figure shows a slice through the middle of the device (y=TSi/2=constant) for different channel doping under a drain bias of 0.7V. The electron Density increases and it is highest in the middle of the channel region and is practically zero at the Si/SiO2; Ge/ZrO2 and Ge/HfO2 interfaces. For gate bias voltage equal to 0.7V as shown in the figure of electron density, the Ge channel electron density with HfO2 and ZrO2 significantly differs from Si channel using SiO2 and takes its maximum when reducing the channel doping. Nanoscience and Nanotechnology 2016, 6(1A): 47-54 51 Channel Doping conc. (cm-3) 0.1×1015 1×1015 10×1015 Table 4. Variation of Gm and Gd with channel doping Gm for HfO2 Gm for ZrO2 Gm for SiO2 Gd for HfO2 Gd for ZrO2 Gd for SiO2 (S) (S) (S) (S) (S) (S) 2378,7 1901.4 1714.11 2391,26 1905,2 1799.2 1750,59 1697,21 1655,9 1056.2 1096 1361.59 910 985.89 1004 1033.17 1016 1400 Channel Doping conc. (cm-3) Witout doping 0.1×1015 1×1015 10×1015 Table 5. Variation of ION with channel doping ION for HfO2 Ge channel A/m ION for ZrO2 Ge channel A/m 1018,2 1025,9 1039,14 1078,86 1035,11 1071,59 1028,11 1070,14 ION for SiO2 Si channel A/m 612.1 734.72 772,21 771.38 SS(mV/decades) 2,2x102 2,0x102 1,8x102 1,6x102 1,4x102 1,2x102 1,0x102 Si channel SiO2 Ge channel HfO2 Ge channel ZrO2 8,0x101 6,0x101 0 2 4 6 8 10 channel doping (cm-3) Figure 4. Subthreshold swing versus Channel doping 16 14 12 Ge,HfO2 10 Ge,ZrO2 8 Si,SiO2 Gm/ ID (V-1) 6 4 2 0 0,0 0,1 0,2 0,3 Vg(V) Figure 5. Gm/ IDS versus Vg for HfO2and ZrO2 with Ge channel and SiO2 with Si channel 52 S. Slimani et al.: Tremendous Opportunities to Improve DGMOSFET by High Mobility Materials Channel Gm(S/m) gd(s/m) 2,5x103 2,0x103 1,5x103 1,0x103 5,0x102 0,0 -1 0 1,4x103 Ge,HfO2 Ge,ZrO2 Si ,SiO2 1,2x103 1,0x103 8,0x102 6,0x102 Si,SiO2 Ge,HfO2 Ge,ZrO2 4,0x102 2,0x102 0,0 -1 0 1 2 3 4 5 6 7 8 9 10 11 channel doping(cm-3) 1 2 3 4 5 6 7 8 9 10 11 channel doping(cm-3) Figure 6. Gm and Gd versus Channel doping 1000 800 ID(A/m) 600 HfO2 ZrO2 400 LG=18nm TGe=6nm 200 Eot=1.1nm SiO2 TSi=6nm 0 0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 VD(V) Figure 7. IDS versus VDS characteristics of DGMOSFETs for HfO2and ZrO2 with Ge channel and SiO2 with Si channel Nanoscience and Nanotechnology 2016, 6(1A): 47-54 53 ratio ION/Ioff IG(A/m) 1,0x104 8,0x103 6,0x103 4,0x103 2,0x103 Ge,HfO2 Ge, ZrO2 Si,SiO2 0 2 4 6 8 10 Channel doping(cm-3) Figure 8. Ratio Ion/Ioffversus channel doping 0,20 Ge channel with ZrO2 Ge channel with HfO2 0,15 Si channel with SiO2 0,10 0,05 0,00 0 2 4 6 8 10 Channel doping( cm-3) Figure 9. Gate current Igversus channel doping 100 10 Doping Gechannel 10x1015 with HfO2 Doping Gechannel 1x1015 with HfO2 DopingGe channel 0.1x1015 with HfO2 1 Doping Gechannel 10x1015 with ZrO2 Doping Gechannel 1x1015 with ZrO2 Doping Gechannel 0.1x1015 with ZrO2 Doping Si channel 10x1015 with SiO2 0,1 Doping Si channel 1x1015 with SiO2 Doping Si channel 0.1x1015 with SiO2 0,01 1E-3 0 The middle of channel LG/2 5 10 15 20 25 30 35 Distance x along source-drain axis (nm) Figure 10. Electron density versus channel doping Electron density (1018 cm-3) 54 S. Slimani et al.: Tremendous Opportunities to Improve DGMOSFET by High Mobility Materials Channel 5. Conclusions In comparison to Si as a channel material, Ge is more desirable. Our calculations predict that Ge channel devices Using the high permitivity has a good control of gate and the drain current increases with the increase of permittivity. We also cannot use high doping because mobility degradation of carrier takes place in the channel region. The increase of permitivity with Ge channel when channel doping was raised improve somme parameters like subthreshold swing and highest output conductance at different values of oxide thickness. Our calculated and simulated results show that the optimized value of channel doping is 1×1015 using ZrO2. ACKNOWLEDGEMENTS The authors would like to thank the support of the Tiziouzou University and also the anonymous reviewers for their critical comments. nextnano: concepts, methods, results, ” J. Comput, Electron, vol. 5, no. 4, pp. 285-289, 2006. [6] M. Sabatil, S. Hackenbuchner, J.A. Majewski, G. Zandler, and P. Vogl, “Towards fully quantum mechanical 3D device simulations,” J.Comput. Electron, vol. 1, no 1/2. pp. 81-85, 2002. [7] . S. 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