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Gaussian distribution of electrical properties of Al / SiO2 / p-Si structure

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  • Save American Journal of M aterials Science 2012, 2(4): 125-130 DOI: 10.5923/j.materials.20120204.05 Gaussian Distribution on Electrical Characteristics of Al/SiO2/p-Si Structures A. B. Selçuk1, S. Bilge Ocak2,*, S. Karadeniz1 1Sarakoy Nuclear Research and Training Centre, 06983 Sar ay, Kazan, Ankara, Turkey 2Gazi University, Atatürk M.Y.O., Çubuk, Ankara Abstract The Al/ /p-Si Schottky diodes (39 dots) with native interfac ia l insulator layer SiO2 we re fabricated on the same Si wafer. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of metal-o xide-semiconductor diodes, which are bas ed on Al/SiO2/p-Si structures, have been meas ured at room temperature. Barrier height (BH), ideality factor (n) of these diodes has been calculated fro m their experimental forward b ias current-voltage (I-V), reverse bias capaci- tance-voltage. Even though they are identically performed on the same quarter Si wafer, the calculated values of BH, wh ich is obtained from I-V characteristic, have ranged fro m 0.687 to 0.772 eV and ideality factor n fro m 1.903 to 4.48. The values of barrier heights obtained from C -V characteristics range fro m 0.629 to 1.097 eV. It was found that the values of barrier height dΦis????????t????r????????i????buotbiotnainoebdtaCin-eVdcfhroamracIt-eVriasntidcsCi-s2 larger than that of these values fro m -V characteristics have been fitted by I-V characteristics. The e xpe rimental va lues BH Gaussian function and their mean values of BHs have been calculated to be 0.730 and 0.863 respectively. Normal d istribution of ideality factors mean value is 3.160 with standard deviation 0.689. Experimental results show that the interface states at a native insulator layer between metal and semiconductor play an important role in the value of the BH, ideality factor and the other electrica l para meters of Schottky d io d es . Keywords Schottky Diodes, MOS, Current-Vo ltage Characteristics, Capacitance-Voltage Characteristics, Gaussian Dis trib u tio n 1. Introduction The elect rical properties of metal-semiconductor (MS), metal-insulator-semiconductor (MIS) Schottky diodes have been investigated because of their importance in electronic device applications[1]. The mechanis ms of carrier transport and some structural parameters of Schottky barrier diodes have been studied both experimentally and theoretically in past decades, but little experimental informat ion are available on Schottky barrier formation and electronic states at metal-semiconductor (MS) interface[2]. It has been generally assumed that the thin insulating layers between the metal and semiconductor is uniform and has distinct effects on the behaviour of MS-diodes. In recent years, there are a vast number of reports on experimental studies of characteristic parameters such as the barrier height (BH) and ideality factor in M S o r, metal-insulato r-semiconductor (MIS) Schottky diodes and solar cells[3]. Also theoretical studies based on the effect of a Gaussian distribution of barrier height (BH) on I-V characteristics have also been reported in literature[4]. * Corresponding author: (S. Bilge Ocak) Published online at Copyright © 2012 Scientific & Academic Publishing. All Rights Reserved The interface qualit ies between the deposited metal and the semiconductor surface determine the performance and reliability of Schottky diodes. Conduction mechanism of MS contact is mainly based on thermionic emission (TE) current model. It is well known that thin insulators between metal and semiconductor affect behavior of the Schottky diode characteristics. Existence of interfacial thin o xide layers between metal and semiconductor may change to electrical characteristics of Schottky diodes by interface state charges[5-7]. Thus, real characteristics of Schottky diodes are affected by interfacial o xide layers[7]. The behaviors of the I-V characteristics of Schottky diodes and MOS diodes describe these effects. Experimental studies of characteristic parameters such as the barrier height and ideality factor in MS and MOS diodes have been widely reported for decades. In addition, effects of Gaussian distribution of the barrier height (BH) and the ideality factors on I-V characteristics have been studied, too. In generally, the BH is likely to be a function of the interface atomic structure, and the inhomogeneity at a MS interface may be caused by grain boundaries, mu ltip le phases, facets, defects, and a mixture of different phases[8,9]. Due to various reasons, calculation of barrier heights has a great importance to determine e lectrica l characteristics in the semiconductor technology. 126 A. B. Selçuk et al.: Gaussian Distribution on Electrical Characteristics of Al/SiO2/p-Si Structures The experimental effective BHs and ideality factors are obtained from I-V and C-V characteristics. These pa= rameters I I 0 exp   q(V − nkT IR    1  − exp   q(V − kT IR)      (1) are different fro m diode to diode even though they are identically prepared[10]. and In the present study, we have calculated barrie r heights of MOS diodes fro m the experimental forward bias cur- = I0 AA*  exp  −  qΦ app kT    (2) rent-voltage and reverse bias capacitance-voltage characteristics of these diodes. Gaussian distribution of barrier height (BH) was obtained fro m C-2-V and I-V characteristics. Additionally, ideality factors were calculated fro m forward bias I-V and the Gaussian distribution of the experimental ideality factors has been acquired fro m I-V characteristics. where ????????0 is reverse saturation current, ???????? is the electron charge, ???????? is the applied voltage, ???????? is the effective diode area, ????????∗ is the effective Richardson constant which is 32 A cm-2K-2, ???????? is the absolute temperature, ???????? is the series resistance, ???????? is the ideality factor and Φ ???????????????????????? is the zero-b ias barrier height. Ideality factor n can be obtained fro m Eq. (1) as 2. Experimental Procedure The semiconductor substrates were boron doped p-type Si single crystals with a (100) surface orientation, 280 µm thick and 1.1 Ωcm resistivity. As the first step, the Si wafer was degreased for 5 min in boiling trichloroethylene, acetone and ethanol respectively. RCA clean ing procedure was applied to the wafer in order to be chemically cleaned (i.e., a 10 min boil in NH3+H2O2+6H2O, followed by a 10 min boil in HCl+H2O2+6H2O), then immersed to diluted HF for 30 s, and finally bathed in deionized water of resistivity 18.3 MΩcm with u ltrasonic vibration and dried by h igh-purity n = q kT   dV d ln I   (3) According to Eq. (3), slope of V versus ln I plot is the ideality factor, interception point of ln I axis, wh ich means zero applied voltage and gives us ln I0 value in linear region above 3kT / q . Then, zero bias barrier height or apparent barrier height can be determined by using Eq. (3). Φ app ln =−   I0 AA*T 2 q / kT   (4) nitrogen. After surface cleaning, high-purity alu miniu m (Al) metal (99.999%) was thermally evaporateod from the tung- sten filament with a thickness of 1500 A onto the back surface of the wafer in vacuum about 2 × 10−6 Torr. Then, temperature t reatment at 500 o C for 3 min in N2 at mosphere was applied to a low-resistivity ohmic contact. The front surface of the Si wafer was exposed to air in a clean glass box for a month at roo m temperature to construct the native oxidation. The rectify ing contacts were formed on the other faces by evaporating alu minum (A l, 99.999%) with a thickness of 1500 A˚ as dots with a diameter of about 1.0 mm through a metal mask at the pressure of 2 × 10−6 Torr. Metal layer deposition rates were monitored with the help of a digital thickness omonitor (FTM 6). The deposition rates were about 10–20 A s-1. Thirty nine dots (Schottky contact) on the same semiconductor surface were performed for the Al/SiO2/p-Si (M OS) Schottky barrier diodes. The I-V measurements were performed using a Keithley 2410 programmable constant current source. The C–V and conductance–voltage (G/ω-V) measurements were performed at various frequencies using an HP 4192A LF impedance analyzer at room temperature in dark at a test signal of 40 mVr ms . The experimental semi-log-forward bias characteristics of Al/SiO2/p-Si SDs are shown in Fig.1. According to the thermionic emission theory, the reverse current o f an ideal Schottky diode should saturate at the value of the expression in Eq.(2). The reverse bias I-V characteristic of the device exhib its an excellent saturation, as seen fro m the figure. Ideality factor and barrier height are calculated by using Eq.(3) and Eq.(4). The BH for Al/SiO2/p-Si SDs fro m the forward bias I-V characteristics has varied fro m 0.687 to 0.772 eV, ideality factor n has varied fro m 1.903 to 4.489. As can be seen, the effective SBH fro m the forward bias I-V characteristics have varied fro m diode to diode. Therefore, it is common practice to take average[14-27]. Figs.2 and 3 show the statistical distribution of BHs and ideality factors fro m the fo rward to bias I-V p lots of the Al/SiO2/p-Si SDs (39 dots), respectively. The experimental d istributions of the effective BHs were fitted by the Gaussian function. The statistical analysis yie lded a mean BH value of 0.73e V with a standard deviation of 0.017eV for the Al/SiO2/p-Si SDs. Furthermore, the experimental d istributions of the ideality factor fitted by the Gaussian function yielded a mean value of 3.160 with a standard deviation of 0.689. Although ideal d iode has an ideality factor as n = 1 , d i- odes are generally greater than unity caused by the effect of 3. Results and Discussion oxide layers, series resistances, inhomogeneities of barrier, etc[28]. One of the reason of barrier inho mogeneities in 3.1. Current-voltage (I-V) characteristics The current through a Schottky barrier diode according to thermionic emission (TE) theory is given by the following relation[11-13] MOS structures may be attributed result of interface defects such as caused by grain boundaries, mu ltip le phases, facets, defects, mixture of different phases, etc[29,30]. These effects cause for ideality factors to have larger values. Thus the inhomogeneities may play an important role and have to be American Journal of M aterials Science 2012, 2(4): 125-130 127 considered in the evaluation of experimental I-V characteristics. As can be seen Fig.4, the BHs become smaller as the ideality factors increase. That is, there is a linear relationship between the experimental effect ive BHs and ideality factors of the Al/SiO2/p-Si SDs. The straight line in Fig.4 is the least squares fit to the experimental data. This finding may be attributed to lateral barrier inhomogeneities of Schottky diodes[16-27]. It has been mentioned that higher ideality factors among identically prepared diodes were often found to accompany lo wer observed BHs. The average BH value of approximately 0.775 eV for Al/ SiO2/p-Si (MIS) d iodes from extrapolation to n=1, will g ive the laterally ho mogeneous BH values. The difference between mean barrier height and lateral ho mogeneous barrier is the value of 0.045 eV. The value of the mean barrier height closes to lateral homogeneous barrier. 1.0E-04 Frequency Mean = 3.160 Std. Dev. = 0.689 1.0E-05 1.0E-06 Current (A) 1.0E-07 1.0E-08 1.0E-09 1.0E-10 -1.5 -0.5 0.5 1.5 Voltage (V) Fi gure 1. Current -Volt age charact erist ics of Al/SiO2/p-Si MOS struct ure Mean = 0.730 eV Std. Dev. = 0.017 eV Ideality Factor, n Figure 3. Distribution of ideality factors obtained from I-V characterist ics of MOS st ruct ures 0.88 0.83 0.78 Barrier Height, Φapp 0.73 0.68 Φapp (n) = -0.0208n + 0.7958 Φapp(1) = 0.775 eV 0.63 0.58 1.0 2.0 3.0 4.0 5.0 Ideality Factor, n Figure 4. Barrier height versus ideality factor plot of Al/SiO2/p-Si MOS st ruct ure Frequency Barrier Height, Φapp (eV) Figure 2. Distribution of barrier heights obtained from I-V characteristics of MOS st ruct ures 3.2. Capacitance -voltage (I-V) characteristics Depletion layer capacitance of the diode is expressed as follow[7-9] C −2 = 2(V0 + V ) qε S A2 N A (5) where ????????0 is the diffusion potential at zero bias which is determined fro m intersection point with V axis of C-2-V graphics, εS is the permittivity of semiconductor, A is the diode area, NA is the acceptor concentration of p-type Si semiconductor which can be obtained fro m slope of the C-2-V plot. Barrier heights from C-V characteristics are determined by 128 A. B. Selçuk et al.: Gaussian Distribution on Electrical Characteristics of Al/SiO2/p-Si Structures Φ=B EF + Vd − ∆ΦB (6) where EF is the Fermi energy level, Vd is the diffusion potential and ∆ΦB is the image force barrier lowering. EF and Vd are given as EF  = kT ln   NV NA    (7) V=d V0 + kT q (8) where band. N V This is the effective density of value for p-type Si substrate states in is 1.73×1 Si 016 valance cm−3 . Image force lowering can be exp ressed as ∆ΦB = qEm 4πε Sε0 (9) where Em is the maximu m electric field and is given by Em =(2 × N A ×Vd / ε S )−1/2 (10) The C-V and C-2-V at 1 MHz at roo m temperature for se- lected 39 Al/ SiO2/p-Si diodes with a native interfacial insulator layer are shown in Fig.5 and Fig.6. When the measurements are carried out at very high fre- quency, the charge at the interface states cannot follow an AC signal[10]. As can be seen fro m Fig.5, for each d iode, the values of capacitance give the peaks about zero bias wh ile the conductance almost increases with increasing voltage. The barrier heights and acceptor carrier concentration values for each diode are obtained from relationship between ca- pacitance-voltage Eq.5. The barrier heights and acceptor carrier concentrations are ranged from 0.629 to 1.097 eV and fro m 3.719×1013 cm-3 to 1.032×1014 cm-3, respectively. As seen from Fig .7 and Fig.8, the experimental distributions of BHs and carrier concentrations are fitted by Gaussian dis- tribution. The statistical analysis of mean BHs and mean carrier concentrations obtained fro m C-2-V plots have yielded as 0.863 eV with standard deviation of 0.104 eV and 6.24 ×1013 cm-3 with standard deviation of 1.777 ×1013 cm-3 , respectively. Mean BH value with stan- dard deviation and mean ideality factor with standard de- viation are obtained fro m the statistical analysis of these parameters. The mean BH and a mean ideality factor values are 0.730 eV with standard deviation 0.017 eV and 3.160 with standard deviation 0.689, respectively. Ideality factor with greater than unity shows that there are series resistance of structure and localized interface states[31,32]. The difference between the mean values of BHs obtained fro m C-V and I-V characteristics 0.133 eV is greater than the mean image force lowering value of 0.007 eV by using Eq. (9). As seen from the mean values, the difference between ΦB (I-V) and ΦB (C-V) for Al/SiO2/p-Si originates fro m the different nature of I-V and C-V measurements. Due to nature of the C-V ande I-V techniques barrier heights deduced fro m them are not always the same. The capacitance C is insensitive to potential fluctuations on a length scale of less than the space charge region and C-V method averages over the whole area and measures to describe BH. Additionally, the discrepancy between the devices may also be exp lained by the existence of an interfacial layer and trap states in s emico n d u cto r. As we know, the effective BHs and ideality factors fro m I-V and C-V measurements varied fro m each individual diode even which are prepared identically[10,18,25,26]. Th is result shows that the potential barrier at semiconductor interfaces depend more strongly on the applied voltage than pred icted by the image-force effect for ideal contacts[17-19]. 4.0E-11 3.5E-11 3.0E-11 Capacitance (F) 2.5E-11 2.0E-11 1.5E-11 Figure 5. st ruct ure 1.0E-11 -1.5 -0.5 0.5 1.5 Voltage (V) Capacitance-Voltage characteristics of Al/SiO2/p-Si MOS 6.5E+21 5.5E+21 4.5E+21 C -2 (F -2) 3.5E+21 2.5E+21 1.5E+21 5.0E+20 -1.5 -0.5 0.5 1.5 Voltage (V) Fi gure 6. C-2-V plot of Al/SiO2/p-Si MOS st ruct ure American Journal of M aterials Science 2012, 2(4): 125-130 129 Mean = 0.863 eV Std. Dev. = 0.104 eV fro m C -V measurement is 0.863  0.104 eV . So, these values can be exp lained by o xide layer and lateral inho mogen eities . This study reveals that the effects such as interface states and insulator layer over I-V and C-V measurements must be taken into account. The main result of this work, although diodes were prepared as possible as identically, they have different characteristics fro m each other. This result shows that the potential barrier at se miconductor interfaces depend more strongly on the applied voltage than predicted by the image-fo rce effect for ideal contacts[16,33]. Therefore, it is common practice to take averages for these values[18,33]. Statistical methods and computations can make mo re confidence results. Frequency Barrier Height, ΦB (eV) REFERENCES Figure 7. Distribution of barrier heights obtained from C-V characteris- [1] V.Janardhanam, A.Ashok Kumar, V.Raanopal Reddy, t ics of MOS st ruct ures P.Narasimha Reddy. J.Alloys Comp.485 (2009) 467. Mean = 6.24x1013 cm-3 Std. Dev. = 1.777x1013 cm-3 [2] K.M aeda, E.Kitahara, Appl. Surf. Sci. 130-132 (1998) 925. [3] H.Bayhan, Kavasoglu A.S. Solid State Electronics 49 (2005) 991. [4] S. Chand, Semicond.Sci.Technolgy 17 (2002)36. [5] P.L.Hanselaer, W.H.Laflere, R.L. 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