eduzhai > Applied Sciences > Engineering >

FPGA Implementation of High Speed Baugh-Wooley Multiplier Using Decomposition Logic

  • Save

... pages left unread,continue reading

Document pages: 7 pages

Abstract: The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.

Please select stars to rate!


0 comments Sign in to leave a comment.

    Data loading, please wait...