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Practical Design of a 10-bits Low Power PWM-based Analog to Digital Converter in a 90 nm CMOS Technology

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Document pages: 15 pages

Abstract: Objective: Analog-to-digital converters (ADCs) bridge the gap between the analog world to digital processing committees and play a vital role in many electronic, biomedical and telecommunication systems. Wireless and portable electronic systems such as smartphones and wearable technologies are the major consumers of these components, which want to increase the accuracy and the speed of their converters as well as reduce power consumption and save battery life. Approach: In this research, three new ideas have been used to design novel ADC: first, to reduce the power consumption, the concept of the gated ring oscillator time-to-digital converter (TDC) is utilized. Then to reduce the quantization noise and increase the oscillation frequency in the ring oscillator, a multi-path connection in the oscillator loop is used. Finally, by employing the pulse width modulation (PWM) method, the designed system is able to increase the speed and accuracy of the converter in the 90 nm MOSFET technology.Main results: The feasibility of the proposed converter is verified by simulations in the circuit level. The resolution of the proposed ADC is 1 LSB= 976.5 µV and maximum power consumption is 1 mW. The result of the INL test was ± 1.2 LSB and the input signal bandwidth was equal to 500 kHz.Significance: The presented architecture is a potential solution for low power converter without sacrificing performance, such as implantable neural signal recording applications.

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