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Design of High Speed and Low-Power NOR Based Dynamic CMOS PLA for Logic Function Realization

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Document pages: 6 pages

Abstract: This paper presents the design of dynamic CMOS PLA for high speed and low power VLSI circuit applications. The design has been carried out based on NOR function. The PLA has been implemented to realize 3 input logic functions using MOS transistor having channel length of 150nm . The circuit is simulated with the help of T-SPICE tools. According to ITRS currently VLSI circuits are designed at power supply voltage (VDD) of ≤ 1 V. In this paper the PLA has been simulated at VDD of 1 V. However the overall power consumption and gate delay of the circuit has been reported for the VDD from 0.5-1.2 V. The power consumption and gate delay of the order of nW and PS respectively. Compared to recent literature in the relevant area our work presented in this paper is also meet the high speed and low power VLSI circuit applications.

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