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Hardware Evaluation of Second Round SHA-3 Candidates Using FPGA

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Document pages: 15 pages

Abstract: The major goal of our paper is that we propose a platform, a design strategy, and evaluation criteria, for a fair and consistent hardware evaluation of FPGA. For portable and home entertainment audio systems, however the general DSP chip-based solution might consume too much power. Then a low-cost and low power solution for this purpose should be sought. There exist two possible approaches that can reduce the chip area and power consumption. One is the simplification of the FIR filter structure, and the other techniques include low power multiplier, adder, memory, supply voltage, etc. In This project we present a low-power FPGA that exploits the low power multiplier design. Power dissipation of integrated circuits is a major concern for VLSI circuit designers. Since power optimization is a major goal of this work we used Window Technique method structure that reduces power consumption over traditional Binary multiplier. Window Technique method is an improved version of tree-based FPGA architecture. In addition, the Booth multiplication algorithms has been modified to include 4:2 compressors that are used to add the partial products generated from the multiplier unit. As 4:2 Compressors reduces number of adders needed in the addition process, it reduces number of full adders needed. Hence this further reduces the power consumption. The Booth multiplication algorithm is implemented using Spartan 3 FPGA from Xilinx, and it could also implement using Application specific Integrated Circuits (ASIC) when further reduction in power consumption is required. The result shows that the proposed architecture is faster than the conventional CMOS architecture, along with reduced power consumption.

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