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A Hardware Approach to Value Function Iteration

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Document pages: 30 pages

Abstract: We propose a novel approach for the computation of dynamic stochastic equilibrium models. We design an FPGA specialized in the computation of a bellman equation via value function iteration (VFI). Our hardware approach documents significant speed gains vis-à-vis GPU-based data-parallelization techniques. The speed gains arise from two layers of parallelism, accessible to hardware developers: instruction-level and pipeline parallelism at logical resources level. By and large, the paper highlights significant computational speed gains from hardware specialization.

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