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Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

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Document pages: 6 pages

Abstract: Power and Area have always been topics of major concern in VLSI. Multipliers and adders form the most vital units for a variety of DSP applications. Hence reducing the power consumption of the multiplier blocks can aid us in reducing the total power consumed by these applications to a large extent. One of the best techniques to do so is by bypassing of the multiplier blocks. Besides bypassing, approximate computing can also help in increasing power and area efficiency for error tolerant applications. This paper aims at designing a multiplier which gives a better performance in terms of area utilization, power consumption and power-delay product as compared to the existing multipliers. Four bypassing techniques namely, Row bypassing, column bypassing, row and column bypassing and two-dimensional bypassing already exist in the literature. These techniques were extensively studied and simulated in Cadence Virtuoso tool, followed by modification of two-dimensional bypassing multiplier using the concepts of approximation and bypassing. Further, validation of results for multimedia and image processing applications is done by obtaining the PSNR values of an image contrasted using the proposed multiplier.

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